package MyIO

import chisel3._
import chisel3.util._

class Setup_Accu(wAddrWidth:Int) extends Bundle{
	val waddr  = Input(UInt(wAddrWidth.W))
	val wen    = Input(Bool())
	val wclear = Input(Bool())
	val lastvec= Input(Bool())
	//when the wen is active, writes dataIn to the waddr if wclear is high;
	//otherwise, it performs an accumulate at the specified address --->  buffer[waddr] += data_in
	//lastvec is a control signal indicating that the operation being stored now is the last vector of a matrix multiplication
}
